The RSX will have 32 shader pipes because ....

[Crossbar]

.... Ken Kutaragi loves the power of two....
Cell has 8 embedded "SPE" CPU cores. What is the basis for this number?

Because it's a power of two, that's all there is to it. It's an aesthetic. In the world of computers, the power of two is the fundamental principle - there's no other way. Actually, in the course of development, there's this one occasion when we had an all-night, intense discussion in a U.S. hotel. The IBM team proposed to make it six. But my answer was simple - "the power of two." As a result of insisting on this aesthetic, the chip size ended up being 221mm2, which actually was not desirable for manufacturing.
http://techon.nikkeibp.co.jp/english/NEWS_EN/20050426/104211/

....and the Nvidia CEO let his tongue slip when talking to eetimes....
Nvidia chief executive officer Jen-Hsun Huang gave few details of the architecture of the RSX chip. He did say, however, that the single 300 million-transistor chip has 32 shading pipelines and is capable of 136 pixel-shader operations per cycle using 128-bit floating-point precision.
http://www.eet.com/news/latest/showArticle.jhtml?articleID=163106181

...but some of them will be disabled,...
But by considering one or two SPEs as a redundancy from the very beginning, we can still use a Cell chip even if it's partially defective," Kutaragi said, who also revealed that a similar scheme would also be used for the PlayStation 3's RSX graphics processor.
http://www.gamespot.com/news/2005/06/20/news_6127799.html

...so it will be less available to the developers, perhaps 28 if they are grouped in quadruples like they are in the 7800 GPU.

Yes, this is speculation, but with some kind of real backing. :uhh:

[Darkon]

Probably

[xbdestroya]

I don't think we ever got more on the validity of that EETimes quote though, since it was the only place to ever get that line. It may be true, but at the same time it may have been a slip on one of their parts; either Jen-Hsun or EETimes. But 32 (28) pipes goes with what I've been expecting, so hey whatever.

[cpiasminc]

Nvidia chief executive officer Jen-Hsun Huang gave few details of the architecture of the RSX chip. He did say, however, that the single 300 million-transistor chip has 32 shading pipelines and is capable of 136 pixel-shader operations per cycle using 128-bit floating-point precision.
Okay... but that's true of the G70 as well. It has 8 vertex pipes and 24 pixel pipes for a total of 32.

Plus each vertex pipe in the G70 can do 1 vector + 1 scalar op (2 ops) per cycle, while each pixel pipe can do 2 vector + 2 scalar + 1 normalize (5 ops) per cycle.

(2 ops * 8 vertex pipes) + (5 ops * 24 pixel pipes) = 16 + 120 = 136 ops per cycle.

On the other hand, if it was 136 pixel shader ops, you have a problem. 136 isn't divisible by 5. It's not divisible by 24, it's not divisible by 28, and it's not divisible by 32.

[xbdestroya]

Uh oh, Sherlock in the house! :)

I'm still aiming for 32 (28) pixel shader pipes on RSX, just because I feel that that's what G71 will contain... and that RSX will be a tweaked G71. But looks like you've taken that EETimes out of the equation Cpi.

[cpiasminc]

I am the ultimate wet blanket after all...

As for 32 pixel pipes... Eh... Well... maybe... I mean that quote does go back to about E3 time, and nVidia was doing its talks on the G7x line. It's entirely possible that G70 itself has 32 pipes for redundancy, and 24 functional happened to be economically feasible for PC hardware, so nVidia expected the same kind of outcome for PS3. Maybe on a 90nm SOI process as Sony's using, the story after all these months passed has turned out different.

But speculating on chance occurrences doesn't provide me with a whole mess of hope.

[Darkon]

Don't you mean shaders processor instead of pipe's ?

[cpiasminc]

Shader pipes, then... or shader pipelines... whatever. I just don't like referring to them as simply "shaders" as "shaders" by itself can also refer to the microcode programs that are sent over to the GPU.

[xbdestroya]

Don't you mean shaders processor instead of pipe's ?

It's somewhat commonly understood that 'pipes' refers to shader pipes, and even more generally to pixel shader pipes; people are prone to further explanation when they mean vertex. It's this propensity to have 'pipes' refer to pixel shader pipelines that is what tripped up people reading Jen-Hsun's quote, whereas Cpi showed that he was refering to the vertex pipes as well.

[Darkon]

It's somewhat commonly understood that 'pipes' refers to shader pipes, and even more generally to pixel shader pipes; people are prone to further explanation when they mean vertex. It's this propensity to have 'pipes' refer to pixel shader pipelines that is what tripped up people reading Jen-Hsun's quote, whereas Cpi showed that he was refering to the vertex pipes as well.


i understood that ...but i always thought that shader processors did those operations not the pipe's themselves I’m confused

[xbdestroya]

i understood that ...but i always thought that shader processors did those operations not the pipe's themselves I’m confused

The shader processors are contained within the pipes - in essence are the pipes - so people just tend to refer to GPUs in terms of pipe counts. Things are beginning slowly to deviate from that sort of easy comparison with chips like R580 and Xenos, but it still serves it's place for expediency, especially when comparing pipe-counts chip to chip all within this assumed G70 architecture derivative.

[Crossbar]

As for 32 pixel pipes... Eh... Well... maybe... I mean that quote does go back to about E3 time, and nVidia was doing its talks on the G7x line. It's entirely possible that G70 itself has 32 pipes for redundancy, and 24 functional happened to be economically feasible for PC hardware, so nVidia expected the same kind of outcome for PS3. Maybe on a 90nm SOI process as Sony's using, the story after all these months passed has turned out different.
I was thinking about pixel shaders, and yes the eetimes story may be some kind of missunderstanding, but what can you do until some new bean spilling starts?

Someone might argue that that many pixel pipes would not match the memory bandwidth or similar.

[frosty]

So, if RSX did get, say, 28 pipes, how would that compare to Xenos GPU?

[liver_kick]

So, if RSX did get, say, 28 pipes, how would that compare to Xenos GPU?

I kinda asked a similar question awhile back. I guess the consensus is that 24 pipes G70 spec @550mhz is likely similar (if not edging out) Xenos spending its entire ALU load on pixel shading (ie without any vertex shading ops), so 28 pipes or more would probably be superior at pixel shading across the board. Dont quote me on that though. ;)

[cpiasminc]

I kinda asked a similar question awhile back. I guess the consensus is that 24 pipes G70 spec @550mhz is likely similar (if not edging out) Xenos spending its entire ALU load on pixel shading (ie without any vertex shading ops), so 28 pipes or more would probably be superior at pixel shading across the board.
Xenos does have vertex shader pipes, it's just that those pipes are the same ones as the pixel shader pipelines. In general, RSX would have more raw pixel shading power than Xenos even with 18 pipes, but that's really based on the theoretical figures. Chances are that the Cg compilers won't really produce code that will effectively maintain that peak 5 ops per cycle in the pixel shaders, though I can imagine 2x vector ops or 2x scalar ops (which is something that Xenos can't do) at a given time is achievable through a large section of a single shader. The per-pipeline vertex shading power of RSX is basically the same as Xenos, but obviously, Xenos could allocate more pipelines at a time to vertex processing if needed. The per-pipeline pixel shading power of RSX is more than double that of Xenos, but they both have some little features that the other can't do. In Xenos' case, most of those differences in pixel shading features happen to be flexibility-related, while in RSX, they're more performance-related.

The main advantage Xenos has in shading performance is hiding latencies on both sides. Things like texture access at the vertex level -- any texture access is high latency, and the problem is that the processing of pixels is always much higher in volume than the processing of vertices. Both GPUs will be able to hide this latency when shading pixels, but Xenos can at least interleave pixel processing threads with vertex processing threads so that it can also hide the latencies better on the vertex side.

[Lekko]

Has anyone considered that the RSX may have more than 32 pipes, but they will be turned off for redundancy? Everyone seems to figure that 32 is the cap, but what if that's the bottom cutoff? Just playing Devil's advocate. (probably wrong, but might as well ask.)

[xbdestroya]

People think 32 is the cap, with redundancy bringing it to 28 possibly, because NVidia's upcoming G71 chip is rumored to have 32 pipes. Pixel pipes for clarity. The theory simply stems from the notion that RSX will be an adapted NVidia design. But sure there's no reason to think RSX couldn't be even larger (unlikely) or a good bit smaller (hope not). It certainly doesn't have to follow the roadmap set by NVidia's desktop line at all in order to adhere to the architecture - it just makes it easier for us to discuss if we do that. :)