Cell Yield Information from IBM

[casualkiss]

http://www.reed-electronics.com/electronicnews/article/CA6350202.html?industryid=21365


Electronic News: Let’s look at design for manufacturability from a different standpoint. IBM has said it needs seven of the eight cores on the Cell processor to work for Sony’s Playstation. Will there be an aftermarket for chips with fewer operational cores?
Reeves: There are a lot of chips with six cores operational, and we’ve been thinking about whether we should really throw all of those away. We also have a separate part number for chips with all eight cores good. The stuff that’s going to be for medical imaging, aerospace and defense and data uses eight cores.

Electronic News: But might it be the less-expensive version of Playstation 3?
Reeves: It could, but I don’t think Sony has thought about offering that. That doesn’t mean there aren’t good uses for a chip with four SPEs [synergistic processing elements].

Electronic News: What’s the defining factor that makes some chips better than others?
Reeves: Defects. It becomes a bigger problem the bigger the chip is. With chips that are one-by-one and silicon germanium, we can get yields of 95 percent. With a chip like the Cell processor, you’re lucky to get 10 or 20 percent. If you put logic redundancy on it, you can double that. It’s a great strategy, and I’m not sure anyone other than IBM is doing that with logic. Everybody does it with DRAM. There are always extra bits in there for memory. People have not yet moved to logic block redundancy, though.

Electronic News: Do any of those cores ever go bad, so that you start out with seven and you wind up with six or five?
Reeves: There’s a reliability failure rate for all chip types. By definition, reliability failure is one point circuit that has failed. If it happens to be in an SPE, it will knock out one of the cores. We have electronic fuses now, rather than laser fuses, which you can only blow when you’re doing wafer tests. Electronic fuses you blow electrically. If you really want to be focused on reliability and up-time availability, you can design one of these chips to self-detect. You can ship it with eight cores working, blow one of them, and from a user perspective you would have self-healed it in the field.

Electronic News: But would it be as fast as the chip with eight cores?
Reeves: Yes, because the Playstation 3 only uses seven of them. You’d have a spare. That isn’t implemented in Cell, but it could be. We implemented that same strategy for IBM systems. If you take a logic hit on a chip, you don’t have any impact on performance because there is enough redundancy built in.

Electronic News: What happens if one of the cores blows on the Sony Playstation 3 if there are only seven to start with?
Reeves: It’s just like a reliability failure on your TV or DVD recorder. If it’s within warranty, you send it back. If it’s not, your game doesn’t work anymore. You’ll always have choices about how reliable you want to make a chip with burn-in. Most chips that go into the consumer marketplace on things such as camcorders or DVD players aren’t burned in. But you can add burn-in and improve reliability 5x to 10x. It’s extra cost. Certainly, a company like Sony adds that in.

Electronic News: How much extra cost?
Reeves: It’s variable. On DRAMs and SRAMs, it’s cents. On processors, because they’re so high-powered, it’s not trivial to power 100 or 1,000 at a time. With all the wattage, it can be dollars.

Electronic News: With the price Sony is going to charge, it can easily add that into the cost.
Reeves: Sony is very concerned about quality and backward compatibility. They want to get this right. They tested game after game after game. When there were about 40 Playstation 1 games that didn’t work properly, that didn’t pass their criteria for quality.

Electronic News: So does that mean the current Playstation 2 systems have a Cell processor?
Reeves: No, they have a 440 Power processor. It’s a 130-nanometer, single-core ASIC chip. It’s the same technology as if you buy a Sony DVD or a Sony Bravia TV. Sony is replacing all the Mips design points with Power design points.



There is more general IBM processor info at the beggining of the article (http://www.reed-electronics.com/electronicnews/article/CA6350202.html?industryid=21365)

[yoshaw]

Good info. Article link not working. Please check

[Red_Eyes]

Reeves: Sony is very concerned about quality and backward compatibility. They want to get this right. They tested game after game after game. When there were about 40 Playstation 1 games that didn’t work properly, that didn’t pass their criteria for quality.

Good to know they're serious about backward compatibility.

[casualkiss]

I guess that whole talk of the Cell having "the highest yields we have ever seen" was um... garbage.

[rpgamer_2k5]

Good to know they're serious about backward compatibility. Agree. I am definitely looking forward to playing Digaea 2 on the PS3. Along with a dozen of PS and PS titles that I have yet to play, like Persona 2. -----Hmm...I wonder how that title is going to play on the PS3, ditto for Vagrant Story. :)

[Insane Metal]

I guess that whole talk of the Cell having "the highest yields we have ever seen" was um... garbage.

They didnt´say that.... they said that the "learning" was the best from all chips they manufactured.

[stanDarsh]

If I am interpreting that correctly, the 10-20% figure is for cell processors with all 8 SPUs working correctly, they did not give a number for 7 SPUs or below.

[cpiasminc]

He said pretty clearly that logic redundancy can double it, which is basically what Sony is doing by reserving 1 SPE for redundancy. It also makes sense that logic redundancy can double it when you consider that the vast majority of your "good" chips are going to be nearer to the center of the wafer (closer to the seed crystal). Since core logic is more sensitive to defects than cache/SRAM/external bus controllers, redundancy there means you can expand the radius of good chips. That radius only needs to increase by 40% in order to double the yields.

Statistically, the first SPE reserved will always have the biggest impact on yields.

[Rukawa]

Cpi,
can you predict Ps3 Cell chip cost to produce?
Assume yield 20-40%, 300mm wafer?
Of course most cost is for ROI on R&D right?

[jaxmkii]

...oh boy here comes the "90% of ps3s fail to start rumors."

[xbdestroya]

I read the logic redundancy to be redundancy in the architecture itself and within the structures rather than as redundancy in terms of the SPE's. It would be great to know if he was talking about yields in terms of 8-SPE chips or what, because I was thinking ~40% yields pre-SPE hit from what he said in the interview.

[pari]

10-20% sounds too low for mass consumer base product. Its acceptable for a low volume product but not for high volume parts.

He said pretty clearly that logic redundancy can double it, which is basically what Sony is doing by reserving 1 SPE for redundancy. It also makes sense that logic redundancy can double it when you consider that the vast majority of your "good" chips are going to be nearer to the center of the wafer (closer to the seed crystal). Since core logic is more sensitive to defects than cache/SRAM/external bus controllers, redundancy there means you can expand the radius of good chips. That radius only needs to increase by 40% in order to double the yields.

Statistically, the first SPE reserved will always have the biggest impact on yields.

The seed crystal is used for growing the silicon ignot or silicon crystal and from this the wafers are cut. Wafers per se do not have any defects, if they do not then they are not used. The defects in the chip occur because of the inherent random nature of the atoms in the process. The steps of building the chip involves varies stages of bombardment of different dopant atoms(Boron or Phosphorous), the angle of the deposit, polishing of the metal, etching of the photoresist, sharpness of the features etched in the photoresist.. and not including the complexicity in building the transistors alone. All these steps and more not mentioned causes the defects in the chip. Its totally impossible to build a perfect chip and all the process target a Gaussian distribution. When the chip is designed, its target frequency coincides with center of the Gaussian distribution of the process. So fast silicon and slow silicon are obtained along with the target frequency.

Logic redundancy to improve the yield kind of sounds vague to me without any specifics. SRAM/Cache are the main killers of the yield because of the smaller transistor size in the bitcells and also they do not follow all the design rules. Also the minimum transistor size for the logic is bigger than the bitcell transistor size. All the test chips for the new process involves building bitcell arrays first even before the logic is put in. In fact all the new process are validated by building the memory array first not the logic block. Test vehicle for new process technology is huge SRAM arrays, PLL and the ominpresent ring oscillator.

The L1 caches have redundant row implemented and this has been standard for a while, so I am not sure what he is saying. And L2 had redundant logic for long time. I agree with Reeves statement that the redundant logic concept came from DRAM but not about the logic redundancy without specifics.

The problem with redundancy for Logic is hard because if one uses Synthesis to syntheses logic then its difficult to replicate the logic unless a duplicate copy of the logic block is placed which is inefficient and defeats the purpose.

The 1 SPE reserved might be for frequency yield, not per se for working chip yield. The Vt variation is becoming more severe, which means chip might not work at the target frequency but would work at reduced frequency. For this 1 SPE reserve makes sense.

can you predict Ps3 Cell chip cost to produce?
Assume yield 20-40%, 300mm wafer?
Of course most cost is for ROI on R&D right?

most of the cost is the equipment and fab cost. To design a chip it might cost about $100 million to $400 million depending upon how long it takes but equipment and process development are high. Equipment cost can be amortized over different process technology but developing process technology is very expensive that cannot be amortized over different process technology.


I read the logic redundancy to be redundancy in the architecture itself and within the structures rather than as redundancy in terms of the SPE's. It would be great to know if he was talking about yields in terms of 8-SPE chips or what, because I was thinking ~40% yields pre-SPE hit from what he said in the interview.

At one point of time IBM was coming up with all kinds of fancy names for electrical fuse in the chip. Again without specifics about what Reeves means about logic redundancy I cannot say one way or another. Most of the times different companies come up with all fancy terms and it takes a while to figure out that its not new stuff.

I would expect the yield percentage to be about 50-60%, with SPE disabled it can be about 70% yield, 90% yield then you are Intel(GOD). This numbers are my guesses based on my experience, which means I can way off the target.

[gljvd]

He said pretty clearly that logic redundancy can double it, which is basically what Sony is doing by reserving 1 SPE for redundancy. It also makes sense that logic redundancy can double it when you consider that the vast majority of your "good" chips are going to be nearer to the center of the wafer (closer to the seed crystal). Since core logic is more sensitive to defects than cache/SRAM/external bus controllers, redundancy there means you can expand the radius of good chips. That radius only needs to increase by 40% in order to double the yields.

Statistically, the first SPE reserved will always have the biggest impact on yields.


Yup thats what he said , however I doubt it actually doubled it . You have a 1x8 design with the spe's being smaller than the main core. Its not even 1/8th of the chip die redudant .

So i think a number closer to 30% would be a good guessing point.

Not bad for a chip that size though. To bad they currently don't have anything to do with the 1x4s as it sounds like they have a ton of them


10-20% sounds too low for mass consumer base product. Its acceptable for a low volume product but not for high volume parts.

The cell chip has been in production for a number of months already , most likely because of bad yields . Doing so would allow them to work on yields while creating usable chips .

that 20-40% sounds good for such a huge chip

Logic redundancy to improve the yield kind of sounds vague to me without any specifics


Well intel celrons used to simply have half the cache turned off , so did the durons to improve yields . They were also lower clocked (though most likely to make more of a performance diffrence)

Ati has in the passed created 16x1 rop cards disabling a quad (4 pipes of that ) and selling it in cheaper cards and using the 16x1 cards as the higher end ones .

This was done mainly with the x800 pro as it was 12 pipes vs the 16 pipe r800xt and xtpe.

[overclocked]

If I am interpreting that correctly, the 10-20% figure is for cell processors with all 8 SPUs working correctly, they did not give a number for 7 SPUs or below.

He didnt give specific numbers about anything Imo. Adding redundancy on complicated designs like Cell and other increase the the yield by 2x and i think thats why he gave such low numbers, ie IBM could only do this slightly PR..


I read the logic redundancy to be redundancy in the architecture itself and within the structures rather than as redundancy in terms of the SPE's. It would be great to know if he was talking about yields in terms of 8-SPE chips or what, because I was thinking ~40% yields pre-SPE hit from what he said in the interview.

Yes thats whas what he said.
I just woke up :sleepy: but its absolutely correct that the redundancy-layout over the whole chip is one thing and redundancy with SPEs a whole other.

[gljvd]

Yes thats whas what he said.
I just woke up but its absolutely correct that the redundancy-layout over the whole chip is one thing and redundancy with SPEs a whole other.


How would this work ? Do you mean two caches for each thin instead of one ?

[The_One]

All these 10%, 20%, 40% and 30% mumble jumbo is making my head spin XD.

[xbdestroya]

The fact that an SPE is disabled... you're confusing the benefit here. It's not that less than 1/8th of the chip is alloted to defects, it's that a defect can occur anywhere on roughly 66% of the chip and the chip still be good to go; the SPE where the defect occurs being the one that gets deactivated.

Cell at 90nm is 221mm^2; G70 when it launched was 334mm^2 on 110nm, and R580 is 315mm^2 on 90nm. So... Cell is hardly the biggest thing out there.

How would this work ? Do you mean two caches for each thin instead of one ?

It's exactly what Intel does (which Reeves seems unsure of); there is redundancy built-in to the memory components of the chip, such that if a defect appears in the cache of the PPE, the chip should be able to go on due to redundant structures. It's the same reason Intel's larger big-cache chips can get such high yields - because they can in fatc tolerate defects that appear in their caches.

[gljvd]

hmm that is correct on the spe haha . Your right

however , from what we are hearing even in this interview , cell yields are not great and while the g70 , r580s are used in other products at cheaper price points , ibm is saying there is no where yet for those 1x4s and I take it 1x6s that are being made , only the 1x8s .

[pari]

Well intel celrons used to simply have half the cache turned off , so did the durons to improve yields . They were also lower clocked (though most likely to make more of a performance diffrence)

Logic redundancy and Cache are two different things. Cache is memory, logic redundancy if I understood correctly meant logic blocks. SPE have 256KB local store memory which is equivalent to L1 Cache.


Ati has in the passed created 16x1 rop cards disabling a quad (4 pipes of that ) and selling it in cheaper cards and using the 16x1 cards as the higher end ones .

This was done mainly with the x800 pro as it was 12 pipes vs the 16 pipe r800xt and xtpe.

Again, without knowing the specifics I would not comment. Disabling logic can be any number of reasons including frequency, Where as you disable half the cache to avoid functional failures at any frequency. The half of the cahce disabled would have bad bits in different column and different row that cannot be covered by redundancy in the cache, so they have to reduce the size of the cache. Again bad bits can be due to any number of reasons in the process, the kind of lead material used for the bumps...

[pari]

Yup thats what he said , however I doubt it actually doubled it . You have a 1x8 design with the spe's being smaller than the main core. Its not even 1/8th of the chip die redudant .

So i think a number closer to 30% would be a good guessing point.

Not bad for a chip that size though. To bad they currently don't have anything to do with the 1x4s as it sounds like they have a ton of them


I agree 1x4 might yield lot more. But yield is all about probability and statistics, and for how many sigmas of process variation the chip is designed. The design for sigma variation is a whole topic on to itself and I cannot talk about it freely. CPI is correct about the first reserve having the most impact on the yield. The new manta is design for manufacturing (DFM) and probabilistic aware circuit design. With this unless the reason for keeping 1 SPE is known its all speculation on our side.

[version]

cell with 8 spe : yield 15% , 100$ per chip
cell with 7 spe: yield 30% , 60$ per chip
cell with 6 spe: yield 70% , 20$ per chip

2 cell with 12 good spe 40$ :), sony push it

[gljvd]

verison , i think you should add alot more to that final cost :-) That 8 spe chip is most likely around a 150$ the 7 spe is most likely around a 110-120$ and the 6 spe chip is most likely around 60-80$

[Rukawa]

Rough numbers from GAF
all estimates
1. Yields average 20% from March until October, so 8 months.
2. Sony allocates 10000 wafers a month at $3000 a wafer.
3. Sony and IBM are using 300mm wafer diameters.
4. The Cell processor is 220mm^2.

To roughly caculate die per wafer:
wafer area / die area - edge of wafer partial die
(wafer diameter/2)^2*pi/(die area) - (wafer diameter)*pi/sqrt(2*die area)
So the total number of Cell's per wafer is (300/2)^2*pi/220-300*pi/sqrt(2*220)=276.

20% of them are good, so you get 55 functional Cell per wafer.

55*10000*8=4.4 million cell chips for launch
At $3000 a wafer, you get $240 million dollars spent total to produce those 4.4 million cells.

If Sony only needs 2.2 million cells, they could run 5000 wafers a month, and only spend $120 million on wafers for Cell before launch.

http://www.neogaf.com/forum/showthread.php?t=109209

[cpiasminc]

I read the logic redundancy to be redundancy in the architecture itself and within the structures rather than as redundancy in terms of the SPE's. It would be great to know if he was talking about yields in terms of 8-SPE chips or what, because I was thinking ~40% yields pre-SPE hit from what he said in the interview.
Could be. Just that when he started talking about "blocks of logic", the first thought in my head was an SPE. I don't know how much real small-block redundancy within cores they have, but it might make some sense given that unlike a lot of PC processors, cache is occupying significantly less than half the die area of CELL.

10-20% sounds too low for mass consumer base product. Its acceptable for a low volume product but not for high volume parts.
True, but... a game console is really that high volume of a part? Sure, you can speak of the tens of millions of PS2 sales, but that's over the entire lifetime of the product up until now. Compared to PC sales which are double that number in the course of a single year. Entirely possible as well is that they're just banking on a shrink to make up costs over the early phases.

1. Yields average 20% from March until October, so 8 months.
2. Sony allocates 10000 wafers a month at $3000 a wafer.
3. Sony and IBM are using 300mm wafer diameters.
4. The Cell processor is 220mm^2.
Did they happen to explain their $3000 per wafer? Sounds like someone is trying to average out the processing cost per wafer, but I would expect more than that if that were the case (unless they're excluding everything post-yield determination). The actual raw wholesale cost of the wafer itself is usually much less, but that's hardly the determinant of cost.

20% of them are good, so you get 55 functional Cell per wafer.
I'd wager a little bit less because the shape of the Cell die is quite rectangular.

[VG Aficionado]

This may be off topic, but I would like to know. My questions are meant to be considered in general terms, this is not just about Cell's case.

What happens to rejected and/or faulty microprocessors? Are they stored, destroyed, buried, processed in some other way? Are they recyclable somehow up to becoming raw materials again? Is it possible to obtain anything from or make other non-commercial uses of microprocessors that are otherwise useless to be included in any device to be sold to the public?

[edoshin]

We do know that cell is anticipated for a wide variety of consumer products including cellphones, and small appliances, so even a single SPE would have some value I would imagine.

[pari]

True, but... a game console is really that high volume of a part? Sure, you can speak of the tens of millions of PS2 sales, but that's over the entire lifetime of the product up until now. Compared to PC sales which are double that number in the course of a single year. Entirely possible as well is that they're just banking on a shrink to make up costs over the early phases.


Other than for Intels,AMDs,.. 10 Million parts/year is big number. The embedded volume would be 100s of k number, from that perspective game console is a high volume part. It just depends upon whom...


Did they happen to explain their $3000 per wafer? Sounds like someone is trying to average out the processing cost per wafer, but I would expect more than that if that were the case (unless they're excluding everything post-yield determination). The actual raw wholesale cost of the wafer itself is usually much less, but that's hardly the determinant of cost.

$3K kind of sounds low but I can definitely be wrong. The cost/wafer is a closely guarded secret which companies would not give out, all part of the competitive advantage.


I'd wager a little bit less because the shape of the Cell die is quite rectangular.

This might sound funny, but the chips are all done with aspect ratio not equal to unity. For some reasons rectangular chips yield better than squarer chips if I remember correct but it could be otherway around. I would check about on Monday... While back when I worked on the team that puts it together, we changed the aspect ratio and do not remember whether it was from Rectangle to square or vice versa. But aspect ratio definitely affects the yield.

[pari]

This may be off topic, but I would like to know. My questions are meant to be considered in general terms, this is not just about Cell's case.

What happens to rejected and/or faulty microprocessors? Are they stored, destroyed, buried, processed in some other way? Are they recyclable somehow up to becoming raw materials again? Is it possible to obtain anything from or make other non-commercial uses of microprocessors that are otherwise useless to be included in any device to be sold to the public?

Its good question, never thought about what they do with the discarded dies, might be they remelt it and use it to make the silicon ignot, remove the metal in the die. Most probably recycled.

When the initial wafers are bad, the chip designers who worked on the chip would all get a whole wafer if the company is generous and if the company is stingy they would all get a die. I have gotten both wafer and die. Before cutting the die, all the tests are done and if the wafer is bad, its scrapped and reused. Also they would stop the lot to make to find the cause of the problem before proceeding, if there are bad wafers to minimize the loss.

[pari]

We do know that cell is anticipated for a wide variety of consumer products including cellphones, and small appliances, so even a single SPE would have some value I would imagine.

I doubt for cellphones, it needs to be about 0.5W or lower, the battery technology has not kept up with the chip technology. So chip power consumption has to be way lower and in order of milliwatts to be used in the cell phones/mobile devices.

[cpiasminc]

This might sound funny, but the chips are all done with aspect ratio not equal to unity. For some reasons rectangular chips yield better than squarer chips if I remember correct but it could be otherway around. I would check about on Monday... While back when I worked on the team that puts it together, we changed the aspect ratio and do not remember whether it was from Rectangle to square or vice versa. But aspect ratio definitely affects the yield.
I seem to remember some talks from Intel folks that they find it better to design as close to square as possible. Obviously, perfect never happens, but the 486 was the classic example of a chip that was very rectangular to begin with and with the second shrink, they worked to get it to a near square. I'm not sure, but I think it wasn't so much of a yield rate thing as much as a volume thing in terms of how many whole dies can even fit on a wafer.

I'd have to find the video again.
EDIT : here we are...
http://www.stanford.edu/class/ee380/Abstracts/040218.html -- abstract
http://www.stanford.edu/class/ee380/ay0304.html -- video on this page (look for the name, "Bob Colwell")
There's also the same presentation at CMU --
http://media2.andrew.cmu.edu/001/ECE-lecture_11-20.wmv

[pari]

I seem to remember some talks from Intel folks that they find it better to design as close to square as possible. Obviously, perfect never happens, but the 486 was the classic example of a chip that was very rectangular to begin with and with the second shrink, they worked to get it to a near square. I'm not sure, but I think it wasn't so much of a yield rate thing as much as a volume thing in terms of how many whole dies can even fit on a wafer.


It has been about 4+yrs for me, so I donot exactly remember the details but remember the aspect ratio talk during the planning stages. I would check it up on Monday. Most of the PowerPC chips have not been square if I remember correctly. I dunno if each company has its own preference.

[overclocked]

Wháts the lenght and height on the latest Cell?

[pari]

I seem to remember some talks from Intel folks that they find it better to design as close to square as possible. Obviously, perfect never happens, but the 486 was the classic example of a chip that was very rectangular to begin with and with the second shrink, they worked to get it to a near square. I'm not sure, but I think it wasn't so much of a yield rate thing as much as a volume thing in terms of how many whole dies can even fit on a wafer.



We do rectangle for our internal reasons, methodology and floorplan architecture and it works for us the best. I cannot say about Intel because they have different methodology and I do not know.

CELL dimension would be available on web, I do not have my ISSCC'05's slides book to get the numbers.

[cpiasminc]

We do rectangle for our internal reasons, methodology and floorplan architecture and it works for us the best. I cannot say about Intel because they have different methodology and I do not know.
Since it is a matter of Sony's manufacturing, I can only look back at the history, and just note that the EE die was very near square. The GS was not quite, but the aspect ratio was around 1.33 (which is not very rectangular at all compared to CELL). I can't recall having seen die photos for PSP, though the GE in the PSP is not that far removed from the GS -- more blend modes, less eDRAM, more texture formats, slower bus.

[pari]

Since it is a matter of Sony's manufacturing, I can only look back at the history, and just note that the EE die was very near square. The GS was not quite, but the aspect ratio was around 1.33 (which is not very rectangular at all compared to CELL). I can't recall having seen die photos for PSP, though the GE in the PSP is not that far removed from the GS -- more blend modes, less eDRAM, more texture formats, slower bus.

CELL is based on IBM design methodology, which is different from SONY and rest of the industry. This has made me curious I need to check other processor die to check the trend. PSP chip was disclosed but not sure about the die photo or dimensions or the conference. All I remember is that SONY did some neat tricks for power savings in the chip, automatic frequency scaling through power supply reduction something like that...

Also with different process technology, the preference for the aspect ratio would also change. The chip was made rectangular pertinent to a process technology and that might not be an issue with either 90nm or 65nm now. All these has to do with controlling the variation in the poly printing which affects the performance and hence the yield.

One sure way to bring the yield to 90+% is to throw more bodies at the process technology and Intel has about 100+ people working on a particular process technology, where the people are analyzing each and every defect in the process to reduce the defect density ratio.

[Xerxes]

....

[cpiasminc]

CELL is based on IBM design methodology, which is different from SONY and rest of the industry.
Sure, but I'd figure since Sony is processing everything PS3-bound on their own soil, they still have the potential to take the IP and "run with it" as they were more or less said to have done with RSX. Sony has had a 90 nm SOI process for a while, so who's to say what they'd do with the layout after all the revisions since the first units that went out their doors or those old pre-XDR prototypes?

All I remember is that SONY did some neat tricks for power savings in the chip, automatic frequency scaling through power supply reduction something like that...
Yes... much to the annoyance of those of us who had to code on it. I loved reading passages that said "Note that the frequency you set with ******SetClockFrequency() will never equal the value you get back from ******GetClockFrequency()." It also ended up saving a lot of power because most of the time, when one device gets clock throttled, they all get throttled. Though a lot of the hair-tearing is due to the fact that the CPU usually gets the short straw when vying for bandwidth.

Also with different process technology, the preference for the aspect ratio would also change.
Possible. Considering that since the 90nm transition, we've gotten EE+GS on a single die and a new IOP and a dual-core CPU for the PSP, though I'm not sure about PSP's GE. Though not being an actual EE, I'd have no clue what the motivation is... PDSOI is something Intel has been deliberately avoiding in favor of skipping straight ahead to FDSOI, so the fact that they're still on bulk probably has a fair bit to do with their preference to stay square.

[pari]

Sure, but I'd figure since Sony is processing everything PS3-bound on their own soil, they still have the potential to take the IP and "run with it" as they were more or less said to have done with RSX. Sony has had a 90 nm SOI process for a while, so who's to say what they'd do with the layout after all the revisions since the first units that went out their doors or those old pre-XDR prototypes?

I am not sure, I thought SONY would start CELL in its own soil for 65nm and 90nm would be done by IBM initially. Then SONY would transition to 65nm at Nagasaki.


Yes... much to the annoyance of those of us who had to code on it. I loved reading passages that said "Note that the frequency you set with ******SetClockFrequency() will never equal the value you get back from ******GetClockFrequency()." It also ended up saving a lot of power because most of the time, when one device gets clock throttled, they all get throttled. Though a lot of the hair-tearing is due to the fact that the CPU usually gets the short straw when vying for bandwidth.

I do not remember the name, I got the hardcopy of the presentation, its something like Dynamic Frequency management. I do not have any idea about the software. Power management stuff is pretty interesting topic currently in the processor design and lots of ideas are being thrown around.


Possible. Considering that since the 90nm transition, we've gotten EE+GS on a single die and a new IOP and a dual-core CPU for the PSP, though I'm not sure about PSP's GE. Though not being an actual EE, I'd have no clue what the motivation is... PDSOI is something Intel has been deliberately avoiding in favor of skipping straight ahead to FDSOI, so the fact that they're still on bulk probably has a fair bit to do with their preference to stay square.

The poly printing is not related to SOI or bulk. PDSOI/FDSOI (partially or fully delepted) is for the state of the body of the transistor. Intel did not want to go SOI route because of the hysteresis due history effect. SOI has reduced gate capacitance compared to BULK but comes with the price tag of floating body which sucks. I have to characterize my stuff for the history effect which I did not do for the BULK(extra work). When one does SenseAmp for the memory in SOI is fun all the way... and a nightmare compared to BULK. I donot even remember the merits/demerits of PD/FDSOI its being a while. I had to read all these stuff about SOI when I transitioned to my present position and I do not even remember them now...

The poly printing is artifact of the fabbing process. Earlier, that is prior to 90nm, the chips had both vertical & horizontal poly. Now a days its only either vertical or horizontal poly, because printing poly in one preferred direction is much easier to do with a very tight tolerance. Poly refers to polysilicon which forms the control gate of the transistor.

The history effect comes into play in SOI because the body is isolated and floating. The charge gets accumulated in the body when the transistor is conducting and since the body is isolated it takes a long time to discharge the accumulated charge. This accumulated charge affects the threshold voltage of the transistor.

Intel has been able to push the BULK much better than IBM/AMD/FREESCALE/TI, now they have strained silicon substrate which gives pretty good boost without neccessity to go to SOI. Strained Silicon is being used in the SOI also, so SOI has the edge over the BULK at the cost of the history effect. There are few other things that can be done in SOI that cannot be done easily in BULK.

Process has become lot complicated and transistor making process has become even more complicated. The number of steps to make a transistor has gone up considerably, as we have to add more and more layers over the transistor layout. Each layer represents one step.

Photolithography has also changed, the shape cut in the mask no longer looks rectangle or square ie no clear straight lines. Post processing is done the shapes to add more shapes around the edges such that with interference of the light print a straight line on the photoresist. Its kind of inverse Fourier Transform, Numerical Technology poineered that and now they are part of synopsys.

[Applefiend]

cell with 8 spe : yield 15% , 100$ per chip
cell with 7 spe: yield 30% , 60$ per chip
cell with 6 spe: yield 70% , 20$ per chip

2 cell with 12 good spe 40$ :), sony push it

Yeah so... Cells with 8 SPEs for medicial uses, super computers
7 SPEs, we know where they go, PS3
6 SPE Cells. In Bravia TVs, DVD players(as decoders), set up boxes. And the combined DVD/TV/Setup/etc market is bigger than the PS3 market, escepially if they're selling them to other manufacturers. Clock those suckers down, maybe you don't need 3.2Ghz to playback an H264 or whatever.

Just like a buffalo, no part is wasted... :)

[cpiasminc]

The poly printing is not related to SOI or bulk.
I was actually referring to the fact that their process techniques are inherently different because they've been putting so much work into pushing bulk further and further. For that matter, they've also been trying to push areal density, and kind of taking more extreme (read : costly) routes in my mind compared to the status quo of MPU foundries elsewhere -- but they're Intel; they can do that. There's way more research going on down there than I can keep track of these days.

Intel did not want to go SOI route because of the hysteresis due history effect.
Well, that's also why they were talking about FDSOI, which has virtually no body history effect (or rather, negligibly small). But unsurprisingly, I believe Intel called it something else in their white papers; "depleted substrate" or something like that.

[gljvd]

Here she is , Miss America .... something something .....

http://www.psxextreme.com/scripts/ps3-scrs//scrbig.asp?fileID=9&scrID=2
http://www.psxextreme.com/scripts/ps3-scrs//scrbig.asp?fileID=10&scrID=2

http://www.psxextreme.com/scripts/ps3-scrs/scr.asp?scrID=2

Doesn't look square to me .

http://www.electronicsweekly.com/Assets/GetAsset.aspx?ItemID=1006


http://www.electronicsweekly.com/Assets/GetAsset.aspx?ItemID=1005

http://www.electronicsweekly.com/Articles/2005/02/07/34385/IBM%2cSony%2cToshibapresentCell.htm

[xbdestroya]

Uh, is there a single person in this thread that seemed ignorant as to whether Cell was rectangular or not? The conversation right now is centering on whether or not the process used for Cell works best with square dies or rectangular dies, not whether Cell itself is rectangular. :smoke:

Anyway for my part, I recall that IBM wanted to go 6-SPEs for yield reasons originally. I forget whether getting more 'square' had anything to do with it (or whether it was 'just' size concerns), but I'll look it up tomorrow I guess.

[pari]

I was actually referring to the fact that their process techniques are inherently different because they've been putting so much work into pushing bulk further and further. For that matter, they've also been trying to push areal density, and kind of taking more extreme (read : costly) routes in my mind compared to the status quo of MPU foundries elsewhere -- but they're Intel; they can do that. There's way more research going on down there than I can keep track of these days.

The foundries are catching up, but Intel/IBM are the leaders in the process technology. That is part of the reason AMD signed up agreement with IBM. Intel pushes the technology by adding more and more steps in the transistor fabbing process. It goes into the area of making source and drain for the transistor and the gate control... the substrate is pushed, there are pushed transistors, now strained substrate which distorts the lattice so that the electrons see lower resistance in the substrate...


Well, that's also why they were talking about FDSOI, which has virtually no body history effect (or rather, negligibly small). But unsurprisingly, I believe Intel called it something else in their white papers; "depleted substrate" or something like that.

True, but FDSOI is more sensitive to process variation, now not only to worry about the Gate length/width variation which affects the channel length, the body thickness variation. In FDSOI the body is thin such that the when the transistor is turned ON, the depletion area is formed in the entire body. So its just trade off one over another. FDSOI works if one can control the process very well. Since Intel is late to the party, they have to come up some name... :) And nobody can beat Intel in coming up with all fancy names for stupid inverters either .. :)

[pari]

Anyway for my part, I recall that IBM wanted to go 6-SPEs for yield reasons originally. I forget whether getting more 'square' had anything to do with it (or whether it was 'just' size concerns), but I'll look it up tomorrow I guess.

XBD, up to 60-70% of the yield is dominated by memories and with redundancy in the memory the yield can be achieved up to 60-70%. Now the rest of the 20+%(there is no 100% yield) is dominated by the random logic. So to fix that it makes sense to make two of the SPE as a redundant logic or back up logic to improve the yield. Theorectically IBM would make CELL with 8SPE but functionally there would be only 6SPE. So this helps IBM improve the yield. Its surprising IBM is having this much difficulty, when Intel gets 90% yield for bigger die size in 90nm.

The square/rectangle was more pertinent when there were vertical&horizontal poly and now its all unidirectional poly. So the aspect ratio might be big factor now, but never know.

[pari]

Nothing particular to CELL, a possible trend. Its PowerPC core rapped around by 1024 smaller cores. IBM is working with the startup company. Another asymmetric processor like CELL.

http://www.tgdaily.com/2006/04/04/ibm_rapport_kilocore/
http://www.rapportincorporated.com/overview.html

[Crossbar]

Anyway for my part, I recall that IBM wanted to go 6-SPEs for yield reasons originally. I forget whether getting more 'square' had anything to do with it (or whether it was 'just' size concerns), but I'll look it up tomorrow I guess.It probably just concerned the die size, remember they also considered to have half the size of the SPEs local store as well.

[overclocked]

This is something i did to make it easy for other members
to join the intruging discussion about yields and numbers, so please post. :thumbl:

Ok, here is some number now that should be around ~98% correct,
So you can make easy yield comparisons and waferstarts @ month for ex.
The Marginal is 2% and its as close i could get.

-First the Cell DD2 at precisely 234mm(dont remember if it was 235mm)
-300mm Wafer
-Optimal layout
-ALL wasted silicon at edges is counted away(hence the 2% error)

The numbers is as given.

Cell-dies that could work ;) should be around 265 per 300mm wafer, soo pick your guess of yield or waferstarts(how long it would take to possibly make X amount of chips etz).

Sorry for the interuption, just want to see if we could get more of the community in.

:cheers:

[xbdestroya]

It probably just concerned the die size, remember they also considered to have half the size of the SPEs local store as well.



Well, this is the quote I *think* I was looking for from a thread back in the day on B3D:

...The number of APU was reduced to 6 from 8 as it was too big for the target cost. The development team progressed the design process with 6 APUs as a precondition. They'd thought they already informed Kutaragi about this decision in a regular report...

Still, I thought the whole 'KK Aesthetics' thing would be a part of that thread as well, and it wasn't.

EDIT: Ok, I found that elsewhere:

Cell has 8 embedded "SPE" CPU cores. What is the basis for this number?

Because it's a power of two, that's all there is to it. It's an aesthetic. In the world of computers, the power of two is the fundamental principle - there's no other way. Actually, in the course of development, there's this one occasion when we had an all-night, intense discussion in a U.S. hotel. The IBM team proposed to make it six. But my answer was simple - "the power of two." As a result of insisting on this aesthetic, the chip size ended up being 221mm2, which actually was not desirable for manufacturing.

In terms of the one-shot exposure area, a size under 185 mm2 was preferable. I knew being oversized meant twice the labor, but I on the other hand, I thought these problems of chip size and costs would eventually be cleared as we go along. But in this challenge of changing the history of computing, I could not possibly accept any deviation from the rule of the power of two. For example, the world of communication also has gone to the rule of the power of ten. Ethernet, which started with 10M bit/s, has gone through stages of 100M and 1G, and 10G is certain to come next. You won't go with, say, 4G just because 10G is technologically difficult. It is my belief that real technological innovation is born from such persistence.


Well, I thought somewhere I had read something about trying to get things more 'square' as well, but I guess not.

Links to the respective ancient threads:

http://www.beyond3d.com/forum/showthread.php?t=20563

http://www.beyond3d.com/forum/showthread.php?t=19139&highlight=aesthetic+Kutaragi

[pari]

Couple of photos showing the next generation transistors.. they are becoming quite wierd looking, gone are days of simple looking transistors.

http://news.com.com/2300-1006_3-6082265-1.html?tag=ne.gall.pg

And the layout would have additional layers over the transistor and few more design rules to obey..

[Crossbar]

"The IBM team proposed to make it six. But my answer was simple - "the power of two." As a result of insisting on this aesthetic, the chip size ended up being 221mm2, which actually was not desirable for manufacturing.
"
Yeah, that was the article I was thinking of, one of my favourites. :)

The thing about that they considered half the size of the SPEs local store (128 kB instead of 256 kB) I learnt from the IBM Cell forum.

[cpiasminc]

Couple of photos showing the next generation transistors.. they are becoming quite wierd looking, gone are days of simple looking transistors.

http://news.com.com/2300-1006_3-6082...tag=ne.gall.pg
Is it just me, or does that look a lot like a FinFET? Well, there are extra gate fins, though I'm not sure what purpose that serves just looking at a photo.

FinFETs --
http://www.hkn.org/imgs/bridge_sp06_figure3.gif
http://www.future-fab.com/assets/images/FF19_wp_parton_fig1.gif

[Smokey]

what are FinFET anyway? but they do look very similar even though i dont know what they are :tardbang:

[pari]

FinFETs are dual gate transistors. The subthreshold leakage current in the transistors have gone up dramatically mainly due to reducing the threshold voltage and other secondary effects. One way to reduce the leakage current is to use dual gate transistors, so FinFETS. This is a short summary

[Heinrich4]

Sorry if posted,

Certain time i read that waffer 300mm^2 cell will be produced cost around US$10000 and each plant (seems they are 2) can work with up to 15000 waffers per month.
Perhaps one cell 15% yield (34 of 228 cell per waffer) costs something as US$250/260 each (2 plants = 1 million per month ?).

[overclocked]

Sorry if posted,

Certain time i read that waffer 300mm^2 cell will be produced cost around US$10000 and each plant (seems they are 2) can work with up to 15000 waffers per month.
Perhaps one cell 15% yield (34 of 228 cell per waffer) costs something as US$250/260 each (2 plants = 1 million per month ?).

Where did you get the 228 likely candidates number from? Im quite sure its around ~265 minus if you see my post above, thanks(i have f$$$$ one paragraph seriously if thats true).

And as to 10000US thats way to high. IIRC the difference between BULK and SOI wafers is not that big either and i heard anywhere from 1300US to 1800US. One number that often come up is around 3000US but i dont know what that includes, Pari maybe have a better idea.

[Heinrich4]

Where did you get the 228 likely candidates number from? Im quite sure its around ~265 minus if you see my post above, thanks(i have f$$$$ one paragraph seriously if thats true).

And as to 10000US thats way to high. IIRC the difference between BULK and SOI wafers is not that big either and i heard anywhere from 1300US to 1800US. One number that often come up is around 3000US but i dont know what that includes, Pari maybe have a better idea.


These 228 numbers of cells per waffer (at 90nm) I read early one year ago, and that I confess can be plus a rumor ( many sites,forums) as well the esteem price of US$10000 each waffers 300mm^2 of cell.

[pari]

Where did you get the 228 likely candidates number from? Im quite sure its around ~265 minus if you see my post above, thanks(i have f$$$$ one paragraph seriously if thats true).

And as to 10000US thats way to high. IIRC the difference between BULK and SOI wafers is not that big either and i heard anywhere from 1300US to 1800US. One number that often come up is around 3000US but i dont know what that includes, Pari maybe have a better idea.

BULK and SOI wafer cost are significantly different, because extra steps are required to make a SOI wafer. There are multiple different ways to make the SOI wafers, the general steps would be, first make the wafer which is similar to the BULK. After that grow oxide over the wafer and sandwich it other wafer. So you have a sandwich Si-SiO2-Si which makes the SOI wafer. So based on the steps taken to the wafers, you end

If the cost of the wafer is not available online, then I cannot say anything as it would confidential for each company.

[overclocked]

BULK and SOI wafer cost are significantly different, because extra steps are required to make a SOI wafer. There are multiple different ways to make the SOI wafers, the general steps would be, first make the wafer which is similar to the BULK. After that grow oxide over the wafer and sandwich it other wafer. So you have a sandwich Si-SiO2-Si which makes the SOI wafer. So based on the steps taken to the wafers, you end

If the cost of the wafer is not available online, then I cannot say anything as it would confidential for each company.

Yes but not to the degree many thinks.
But i see that i wasnt clear with that sentence as the pricefigures where meant to be for SOI wafers only.

These 228 numbers of cells per waffer (at 90nm) I read early one year ago, and that I confess can be plus a rumor ( many sites,forums) as well the esteem price of US$10000 each waffers 300mm^2 of cell.

Ok, i thought that sounded very expensive. :)

[cpiasminc]

IIRC the difference between BULK and SOI wafers is not that big either and i heard anywhere from 1300US to 1800US. One number that often come up is around 3000US but i dont know what that includes, Pari maybe have a better idea.
I've seen a few prices for wafers in public whitepapers from various companies like Isonics and such, but those are all for sale of wafers themselves. The cost of a wafer is very small -- if you're looking only at purchase price -- I myself could pay for the cost of one bulk wafer out of pocket and think nothing of it. Though the fact that they're only sold in large lots kind of kills that if you wanted to go buying wafers. It's the process of doing something with a wafer that's expensive.

The purchase price difference between SOI and bulk is a pretty huge ratio, but on the scale of processing costs, it's small (slightly smaller than the numbers you say, assuming all other costs are equal). For a chip the size of CELL (even at 10% yields) the wafer cost alone probably only makes about a $3 cost difference.

Figures like the $3000 or $10000 a wafer are more meant to be rough guesses at the cost of actually running a wafer through the fab. I think $3000 sounds rather low, though. I'd guess they're not including costs which are variable with respect to yield.

[pari]

I've seen a few prices for wafers in public whitepapers from various companies like Isonics and such, but those are all for sale of wafers themselves. The cost of a wafer is very small -- if you're looking only at purchase price -- I myself could pay for the cost of one bulk wafer out of pocket and think nothing of it. Though the fact that they're only sold in large lots kind of kills that if you wanted to go buying wafers. It's the process of doing something with a wafer that's expensive.

The purchase price difference between SOI and bulk is a pretty huge ratio, but on the scale of processing costs, it's small (slightly smaller than the numbers you say, assuming all other costs are equal). For a chip the size of CELL (even at 10% yields) the wafer cost alone probably only makes about a $3 cost difference.

Agree, processing the wafer is much more expensive than the wafer itself, when doing higher quantity even the wafer cost counts. Initially when SOI processors were being introduced, the cost of wafer counted against it. FYI, Motorola(Freescale) was the first to market SOI microprocessor. Now AMD/IBM/Freescale do SOI microprocessors, rest still doing BULK, I am not sure about TI yet.


Figures like the $3000 or $10000 a wafer are more meant to be rough guesses at the cost of actually running a wafer through the fab. I think $3000 sounds rather low, though. I'd guess they're not including costs which are variable with respect to yield.

I would guess about $10000 minimum per wafer including the processing cost which accounts for the yield. I have wafers which could have potentially yielded $40-$50K five years back, if all the dies worked and of course none of them work...

[overclocked]

Just an ex a Athlon 64 wafer going from start to finish is like 500 different stations, so i think thats why numbers are rather pointless cause it paints so little of the whole picture ,in that sence its meaningless.

Thank god we have a good journalist at the Shitquirer to bend this subjects out for us.. ;)

[yoshaw]

Already posted?

Nevertheless, interesting and contrasting(to usual negative) take on Cell Yield. Notice the bold parts too.

Cell processor producers Sony, Toshiba and IBM are getting rather low-sounding yields of the broadband-oriented CPU it seems - at least if comments made by Tom Reeves, VP of semiconductor and technology services at IBM, are anything to go by.

....Tom said a number of other interesting things, one of which was: "With a chip like the Cell processor, you’re lucky to get 10 or 20 per cent [yields]." He compared that will the yields achieved with smaller, more basic chips, which can reach 95 per cent.

In other words, Cell yields are tiny, right? That's certainly what a number of sites have concluded, and while we'd pause before suggesting Cell yields are high - it's a new processor architecture, so they're not likely to be - it's worth waiting before you sell all your Sony shares and buying Microsoft stock.

.... Reeves' figure is likely to centre on the top-grade chips, so the number of suitably operational PS3-oriented parts coming off the production line is likely to be higher - and will continue to rise, in all probability, as more wafers are completed and the Cell partners continue to refine the process.

Sony has said it expects to sell 6m PS3s by March 2007, roughly four and a half months after the mid-November 2007. Given the size of a Cell die - approximately 221mm² - and the size of a 300mm wafer, IBM and co. are going to get no more than 320 Cells per wafer, ignoring the fact that the wafer's round and the die is rectangular.

At 20 per cent yield, that's 64 Cells per wafer, so Sony needs 93,7500 wafers to in 4.5 month to get enough Cells. That's 20,833 wafer starts per month, which isn't entirely out of order, given not only IBM but Sony will be producing Cells destined for PS3s.

But the issue here is not entirely one of numbers - it's about cost too. The lower the yield the more wafers needed, and the higher the cost of each suitable processor. But since Sony doesn't expect the PS3 hardware to be profitable for some years, it should be able to cope with that. That leaves it banking on not only improving yields - to help reduce manufacturing costs - but also buoyant games sales, which is where it will make its money in the early days, to pull the system into profitability. These trends are a given in the console business, and there are plenty of other factors than Cell yield that Sony can tweak on its PS3 profit/loss spreadsheet to help turn the Total cell from red to black.

http://www.reghardware.co.uk/2006/07/13/ibm_sony_cell_yield_revelation/

[venomv]

I think I have asked this question before, but why are wafers round? Seems like a waste to me.

[Crossbar]

I think I have asked this question before, but why are wafers round? Seems like a waste to me.
It's just because the wafers are cut from a single silicon crystal and that crystal is round just because of the method used when growing the crystal,

http://img80.imageshack.us/img80/4900/czochralski1kleinum3.gif (http://imageshack.us)

described in detail here:
http://www.tf.uni-kiel.de/matwis/amat/elmat_en/kap_6/illustr/i6_1_1.html

[venomv]

Oh, that makes sense.

[overclocked]

Already posted?

Nevertheless, interesting and contrasting(to usual negative) take on Cell Yield. Notice the bold parts too.


Amazing that they can publish something with so much errors in that sister-site also, bleh.. :rant: